# yaml -rw-r--r-- 7.3 KiB View raw
                                                                                
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---

$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Devicetree bindings for the Adreno or Snapdragon GPUs

maintainers:
  - Rob Clark <robdclark@gmail.com>

properties:
  compatible:
    description: |
      The driver is parsing the compat string to figure out the gpu-id and patch level.
    oneOf:
      - items:
          - pattern: '^qcom,adreno-[3-6][0-9][0-9]\.[0-9]$'
          - const: qcom,adreno
      - items:
          - pattern: '^amd,imageon-200\.[0-1]$'
          - const: amd,imageon

  clocks:
    minItems: 0
    maxItems: 7

  clock-names:
    minItems: 0
    maxItems: 7

  reg:
    minItems: 1
    maxItems: 3

  reg-names:
    minItems: 1
    maxItems: 3
    items:
      - const: kgsl_3d0_reg_memory
      - const: cx_mem
      - const: cx_dbgc

  interrupts:
    maxItems: 1

  interrupt-names:
    maxItems: 1

  interconnects:
    minItems: 1
    maxItems: 2
    description: |
      optional phandle to an interconnect provider. See
      ../interconnect/interconnect.txt for details.
      Some A3xx and all A4xx platforms will have two paths;
      all others will have one path.

  interconnect-names:
    minItems: 1
    maxItems: 2
    items:
      - const: gfx-mem
      - const: ocmem
    description: |
      the names of the interconnect paths that correspond to
      the interconnects property

  iommus:
    maxItems: 1

  sram:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    minItems: 1
    maxItems: 4
    description: |
      phandles to one or more reserved on-chip SRAM regions.
      phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
      a4xx Snapdragon SoCs. See
      Documentation/devicetree/bindings/sram/qcom,ocmem.yaml

  operating-points-v2: true
  opp-table: true

  power-domains:
    maxItems: 1

  zap-shader:
    type: object
    description: |
      For a5xx and a6xx devices this node contains a memory-region that
      points to reserved memory to store the zap shader that can be used to
      help bring the GPU out of secure mode.
    properties:
      memory-region:
        $ref: /schemas/types.yaml#/definitions/phandle

      firmware-name:
        description: |
          Default name of the firmware to load to the remote processor.
    required:
      - firmware-name

  "#cooling-cells":
    const: 2

  qcom,gmu:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: |
      for GMU attached devices a phandle to the GMU device that will
      control the power for the GPU


required:
  - compatible
  - reg
  - interrupts

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$'

    then:
      properties:
        clocks:
          items:
            enum:
            - description: GPU Core clock
            - description: GPU Interface clock
            - description: GPU Memory clock
            - description: GPU Memory Interface clock
            - description: GPU Alternative Memory Interface clock
            - description: GPU 3D engine clock ?
            - description: GPU RBBM Timer for Adreno 5xx series
          minItems: 2
          maxItems: 7

        clock-names:
          items:
            enum:
            - const: core
            - const: iface
            - const: mem
            - const: mem_iface
            - const: alt_mem_iface
            - const: gfx3d
            - const: rbbmtimer
          minItems: 2
          maxItems: 7

      required:
        - clocks
        - clock-names
  - if:
      properties:
        compatible:
          contains:
            pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'

    then: # Since Adreno 6xx series clocks should be defined in GMU
      properties:
        clocks:
          maxItems: 0

        clock-names:
          maxItems: 0

examples:
  - |

    // Example a3xx/4xx:

    #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
    #include <dt-bindings/clock/qcom,rpmcc.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    gpu: gpu@fdb00000 {
        compatible = "qcom,adreno-330.2", "qcom,adreno";

        reg = <0xfdb00000 0x10000>;
        reg-names = "kgsl_3d0_reg_memory";

        clock-names = "core", "iface", "mem_iface";
        clocks = <&mmcc OXILI_GFX3D_CLK>,
                 <&mmcc OXILICX_AHB_CLK>,
                 <&mmcc OXILICX_AXI_CLK>;

        interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "kgsl_3d0_irq";

        sram = <&gpu_sram>;
        power-domains = <&mmcc OXILICX_GDSC>;
        operating-points-v2 = <&gpu_opp_table>;
        iommus = <&gpu_iommu 0>;
        #cooling-cells = <2>;
    };

    ocmem@fdd00000 {
        compatible = "qcom,msm8974-ocmem";

        reg = <0xfdd00000 0x2000>,
              <0xfec00000 0x180000>;
        reg-names = "ctrl", "mem";

        clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
                 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
        clock-names = "core", "iface";

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0 0xfec00000 0x100000>;

        gpu_sram: gpu-sram@0 {
            reg = <0x0 0x100000>;
        };
    };
  - |

    // Example a6xx (with GMU):

    #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
    #include <dt-bindings/power/qcom-rpmpd.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interconnect/qcom,sdm845.h>

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;

        zap_shader_region: gpu@8f200000 {
            compatible = "shared-dma-pool";
            reg = <0x0 0x90b00000 0x0 0xa00000>;
            no-map;
        };
    };

    gpu@5000000 {
        compatible = "qcom,adreno-630.2", "qcom,adreno";

        reg = <0x5000000 0x40000>, <0x509e000 0x10>;
        reg-names = "kgsl_3d0_reg_memory", "cx_mem";

        #cooling-cells = <2>;

        interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

        iommus = <&adreno_smmu 0>;

        operating-points-v2 = <&gpu_opp_table>;

        interconnects = <&rsc_hlos MASTER_GFX3D &rsc_hlos SLAVE_EBI1>;
        interconnect-names = "gfx-mem";

        qcom,gmu = <&gmu>;

        gpu_opp_table: opp-table {
            compatible = "operating-points-v2";

            opp-430000000 {
                opp-hz = /bits/ 64 <430000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                opp-peak-kBps = <5412000>;
            };

            opp-355000000 {
                opp-hz = /bits/ 64 <355000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                opp-peak-kBps = <3072000>;
            };

            opp-267000000 {
                opp-hz = /bits/ 64 <267000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                opp-peak-kBps = <3072000>;
            };

            opp-180000000 {
                opp-hz = /bits/ 64 <180000000>;
                opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
                opp-peak-kBps = <1804000>;
            };
        };

        zap-shader {
            memory-region = <&zap_shader_region>;
            firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
        };
    };